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        <td id="breadcrumbs"><span style="text-transform: uppercase;"><a href="http://www.purdue.edu/">Purdue</a> > <a href="/Engr/">Engineering</a> > <a href="/OOSD">Object-Oriented Software Development</a> > <a href="/OOSD/F2012">F2012</a> > <strong><a href="/OOSD/F2012/Exercises">Exercises</a></strong></span></td>
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  <h2 style="text-align: center;">
	ECE 264 Exercise 1 - Due August 28th, 2012 @ 6:00pm</h2>
<h2 style="text-align: center;">
	Makefile</h2>
<h2>
	Advantages of Multiple Files</h2>
<p>
	It is impossible to write a C program using a single file. When you include a header file, you are already using multiple files.You do not implement printf, do you? Where does it come from? It comes from C libraries, such as libc.so in /usr/lib/. Why is C designed in this way?&nbsp; What are the advantages of writing a program using multiple files?</p>
<ul>
	<li>
		Reduce redundant work.&nbsp; Many frequently used functions are supported by libraries. You don&#39;t have to write your own printf, scanf, or fopen.</li>
	<li>
		Improve portability. Some functions handle low-level activities related to hardware, such as reading files from a disk or sending packets through a network. It is better to isolate the hardware-specific in libraries so that your program can run on different computers, as long as your program uses the correct libraries (usually need to recompile the source code).</li>
	<li>
		Enhance performance. Libraries are well optimized so your program can have better performance.</li>
	<li>
		Partition work for collabortion. When you write a large program with other people, it is natural to break the work into smaller units. Each of you is responsibile for some units. Each unit is stored in a single file.</li>
	<li>
		Save compilation time. Compiling a large program can take hours. If the whole program is in a single file and you change only one line, you have to wait for hours to check whether your change is correct. A better solution is to break the program into many files and compile only the files affected by your change. Then the object files are linked. This may take a few seconds, much better than a few hours.&nbsp;</li>
</ul>
<p>
	The last advantage is critical in developing large programs. This is an important reason to separate compilation from linking.</p>
<h2>
	Makefile</h2>
<p>
	Even though there are so many advantages using multiple files, nobody is patient enough to type &quot;gcc -c file1.c ... gcc -c file2.c ...&quot; every time. Fortunately, there are many tools to help, among them is <a href="http://www.gnu.org/software/make/manual/make.html">make</a>. This is a UNIX command and by default, it takes an input file called <b>Makefile</b>. This exercise explains how to write simple Makefiles.</p>
<p>
	Download the <a href="./ex1.zip">code</a> used in this exercise. It consists of two programs:</p>
<ul>
	<li>
		Program 1 - consists of the file main1.c</li>
	<li>
		Program 2 - consists of the files main2.c f1.c f1.h f2.c f2.h</li>
</ul>
<p>
	Use the command &quot;unzip&quot; to extract the files.</p>
<p>
	The following is a basic Makefile to compile and link program2.</p>
<pre>
ex1: main2.o f1.o f2.o
	gcc -Wall -Wshadow main2.o f1.o f2.o -o ex1

main2.o: main2.c f1.h f2.h
	gcc -Wall -Wshadow  -c main2.c

f1.o: f1.c f1.h
	gcc -Wall -Wshadow  -c f1.c

f2.o: f2.c f2.h
	gcc -Wall -Wshadow  -c f2.c

clean:
	rm *.o ex1
</pre>
<p>
	Type the above code into a file called <i>Makefile</i> and save it. Before &quot;gcc&quot;,<span style="background-color:#ffff00;"> </span><strong><span style="background-color:#ffff00;">it is TAB, not space</span></strong><span style="background-color:#ffff00;">.</span></p>
<p>
	You should always have</p>
<pre>
 -Wall -Wshadow 
</pre>
<p>
	after gcc. They will give you warning messages that likely come from errors.</p>
<p>
	The first line means the program ex1 depends on three files: main2.o, f1.o, and f2.o. A .o file is called an object file. If these three files are available, the second line uses gcc to <b>link</b> the three object files and create the executable called ex1.&nbsp; Please notice that the command gcc is after a<span style="color: rgb(255, 0, 0);"><b> TAB, not space</b></span>. How are the three object files are created? They are created by the following three rules. The file main2.o requires three files: main2.c, f1.h, and f2.h. The following line uses gcc to <b>compile</b> (with the -c flag) main2.c and create the object file main2.o.&nbsp; The same situation applies to f1.o and f2.o.&nbsp; How do you use Makefile? Simply type</p>
<p>
	<i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; make</i></p>
<p>
	and you will see the following messages</p>
<pre>
gcc -Wall -Wshadow -c main2.c
gcc -Wall -Wshadow -c f1.c
gcc -Wall -Wshadow -c f2.c
gcc -Wall -Wshadow main2.o f1.o f2.o -o ex1
</pre>
<p>
	&nbsp;</p>
<p>
	You can execute the program by typing</p>
<p>
	<i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ./ex1</i></p>
<p>
	What is so important about Makefile? It is the dependence rules.</p>
<pre>
ex1: main2.o f1.o f2.o
</pre>
<p>
	says that the executable main depends on main.o, f1.o, and f2.o. If any of the three object files has been changed, execute the following command</p>
<pre>
	gcc -Wall -Wshadow main.o f1.o f2.o -o main</pre>
<p>
	How does make know whether f1.o has changed? It checks the following rule</p>
<pre>
f1.o: f1.h f1.c
</pre>
<p>
	If f1.h or f1.c is changed, execute the following command</p>
<pre>
	gcc -Wall -Wshadow -c f1.c
</pre>
<p>
	If neither f1.h nor f1.c has changed, then f1.c will not be compiled. How does the computer know whether a file has been changed? It compares the time of the files. If f1.c&#39;s time is later than f1.o&#39;s time, make thinks f1.c has been changed and generates a new f1.o.&nbsp; If you the following command</p>
<p>
	<i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; touch f1.c</i></p>
<p>
	the time of f1.c is set to the current time and it is later than f1.o&#39;s time. Now, type</p>
<p>
	&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<i> make</i></p>
<p>
	again and you will see the following message</p>
<pre>
gcc -c f1.c
gcc -Wall -Wshadow main.o f1.o f2.o -o ex1
</pre>
<p>
	The message means that f1.c is compiled again and a newer version of main is created. Notice that f2.c is not recompiled. This saves time.&nbsp; If a file has not changed, it is unnecessary to compile it again.&nbsp; The last rule says, if you type</p>
<p>
	<i>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; make clean</i></p>
<p>
	the object files and main are deleted.</p>
<p>
	In Makefile, anything after # is treated as a comment.</p>
<h2>
	Define Symbols</h2>
<p>
	We can define symbols in Makefile. For example</p>
<pre>
GCC = gcc
CFLAGS = -Wall -Wshadow

ex1: main2.o f1.o f2.o
	$(GCC) $(CFLAGS) main2.o f1.o f2.o -o ex1

main2.o: main2.c f1.h f2.h
	$(GCC) $(CFLAGS) -c main2.c

f1.o: f1.h f1.c
	$(GCC) $(CFLAGS) -c f1.c

f2.o: f2.h f2.c
	$(GCC) $(CFLAGS) -c f2.c

clean:
	rm *.o ex1
</pre>
<p>
	If we decide to use another compiler, we can change this line</p>
<pre>
GCC = gcc
</pre>
<p>
	without changing any other lines because GCC is substituted in the following lines. We can also change the flags by adding -g for debugging or -O for optimization.</p>
<p>
	We can also create a symbol OBJS that represents all object files:</p>
<pre>
GCC = gcc
CFLAGS = -Wall -WShadow
OBJS = main2.o f1.o f2.o 
ex1: $(OBJS)
	$(GCC) $(CFLAGS) $(OBJS) -o ex1

main2.o: main2.c f1.h f2.h
	$(GCC) $(CFLAGS) -c main2.c

f1.o: f1.h f1.c
	$(GCC) $(CFLAGS) -c f1.c

f2.o: f2.h f2.c
	$(GCC) $(CFLAGS) -c f2.c

clean:
	rm *.o ex1
</pre>
<p>
	&nbsp;</p>
<h2>
	Special Symbols</h2>
<p>
	You can use $@ in the second line to replace the name before : in the first line.&nbsp; The previous Makefile is equivalent to the following</p>
<pre>
GCC = gcc
CFLAGS = -Wall -Wshadow
OBJS = main2.o f1.o f2.o

ex1: $(OBJS)
	$(GCC) $(CFLAGS) $(OBJS) -o $@

main2.o: main2.c f1.h f2.h
	$(GCC) $(CFLAGS) -c main2.c -o $@

f1.o: f1.h f1.c
	$(GCC) $(CFLAGS) -c f1.c -o $@

f2.o: f2.h f2.c
	$(GCC) $(CFLAGS) -c f2.c -o $@

clean:
	rm *.o ex1
</pre>
<p>
	&nbsp;</p>
<p>
	There are three object files and we have list main.o, f1.o, and f2.o separately. This is somewhat tedious. A solution is to use symbol substitution rule in Makefile.</p>
<pre>
GCC = gcc
CFLAGS = -Wall -Wshadow
OBJS = main2.o f1.o f2.o

ex1: $(OBJS)
	$(GCC) $(CFLAGS) $(OBJS) -o $@

.c.o: 
	$(GCC) $(CFLAGS) -c $*.c 
</pre>
<p>
	The last two lines tell make that &quot;If you want an object file, compile a .c file of the same name.&quot;</p>
<h2>
	makedepend (OPTIONAL)</h2>
<p>
	This Makefile is, unfortunately, wrong. If you modify f1.h and type <i>make</i>, you will see</p>
<p>
	make: `main&#39; is up to date.</p>
<p>
	One solution is to use the makedepend command. Modify Makefile as follows</p>
<pre>
GCC = gcc

CFLAGS = -Wall -Wshadow

SRCS = main2.c f1.c f2.c
OBJS = main2.o f1.o f2.o

ex1: $(OBJS)
	$(GCC) $(CFLAGS) $(OBJS) -o $@

.c.o: 
	$(GCC) $(CFLAGS) -c $*.c 

clean:
	rm *.o ex1

depend:
	makedepend $(SRCS)
</pre>
<p>
	Type <i> make depend</i> and the required header files are listed in Makefile. If you modify f1.h, main.c and f1.c will be recompiled and main will be linked again.</p>
<p>
	You do not to include makedepend into the Makefiles that you submit for this exercise.</p>
<h2>
	Makefiles and Multiple Programs</h2>
<p>
	You can using a single makefile to compile mutliple programs. &nbsp;Here is an example of a makefile that could be used to compile Program 1 and Program 2.</p>
<p>
	&nbsp;</p>
<pre>
GCC = gcc
CFLAGS = -Wall -Wshadow

main1: main1.c
        $(GCC) $(CFLAGS) main1.c -o ex1

main2: main2.o f1.o f2.o
	$(GCC) $(CFLAGS) main2.o f1.o f2.o -o ex1

main2.o: main2.c f1.h f2.h
	$(GCC) $(CFLAGS) -c main2.c

f1.o: f1.h f1.c
	$(GCC) $(CFLAGS) -c f1.c

f2.o: f2.h f2.c
	$(GCC) $(CFLAGS) -c f2.c

clean:
	rm *.o ex1</pre>
<p>
	&nbsp;</p>
<p>
	If you typed&nbsp;<em>make&nbsp;</em>in the command prompt,&nbsp;you would compile the first section in the makefile, main1. &nbsp; &nbsp;However, if you wanted to compile program2, just typing <em>make</em> would not accomplish this task. &nbsp;&nbsp;It can be done by typing the following at the command prompt</p>
<p style="margin-left: 40px; ">
	<em>make main2</em></p>
<p>
	With this command, the makefile will start its compilation at the section of the makefile named main2. &nbsp;&nbsp;</p>
<p>
	&nbsp;</p>
<h2>
	Beyond Makefile</h2>
<p>
	Every programmer has to know make, at least understands its purpose and basic principles. There are many features not covered in this exercise. Some tools can inspect your source code structure and automatically generate Makefile. New tools are being develped to replace or improve make. For example, some Java programs are built using <a href="http://ant.apache.org/">ant</a>.</p>
<h2>
	What to Submit?</h2>
<p>
	&nbsp;A .zip file containing a single Makefile that compiles both programs, f1.c, f1.h, f2.c, and f2.h.</p>
<p>
	The testing server server will run two commands:</p>
<ul>
	<li>
		make main1 - compiles program 1 and generates an executable called &#39;ex1&#39;.</li>
	<li>
		make main2 - compiles program 2 and generates an executable called &#39;ex1&#39;.</li>
</ul>
<p>
	In your Makefile, please use the following names for the sections that compile program 1 and link the object files of program 2:</p>
<ul>
	<li>
		Program 1 - main1</li>
	<li>
		Program 2 - main2</li>
</ul>
<p>
	You can read how to submit your assignment <a href="/OOSD/F2012/html/submission.html">here.</a></p>
<p>
	If you receive the follwing message during your submission</p>
<p style="margin-left: 40px; ">
	<em>Compiliation Error Occurred! No Executable ex1 is generated! This may due to syntax error or wrong target name</em></p>
<p>
	It means that your Makefile did not properly compile your program. &nbsp;Please check the name of the sections in your Makefile and make sure they match the names given above.&nbsp;</p>
<h2>
	FAQ</h2>
<p>
	Q: Why do we need to learn Makefile?</p>
<p>
	A: Makefile is widely used to compile complex programs. You really don&#39;t want to type &quot;gcc ...&quot; so many times.</p>
<p>
	Q: Is Makefile just a quick way to compile programs?</p>
<p>
	A: Makefile detects which files have been changed and compile only these files. When you are developing a large program, you don&#39;t want to compile everything if you change only one line in a single file. Compiling a complex program (such as Linux kernel) may take hours.</p>
<p>
	Q: What are the advantages of the flags?</p>
<p>
	A: They can be applied to all files consistently.</p>
<p>
	Q: Do we need to write Makefile by hand for every program?</p>
<p>
	A: There are tools to generate Makefile, for example <a href="http://www.airs.com/ian/configure/">GNU configure</a>. Eclipse and qmake can also create Makefile.</p>
<p>
	Q: What happens if the dependence in Makefile is wrong?</p>
<p>
	A: If there are unnecessary depenence, more files will be recompiled unnecessarily and this wastes time. If a dependence is missing, some needed files are not recompiled and the executable can be incorrect.</p>
<p>
	Q: To prevent missing dependence, can I just do &quot;make clean&quot; every time before &quot;make&quot;?</p>
<p>
	A: Yes, for small programs. For large programs, you don&#39;t want to wait for hours compiling files unnecessarily.</p>
<p>
	Q: Can Makefile be used to compile programs only?</p>
<p>
	A: Makefile can be used to handle other types files. For example, if you are writing a report that includes several latex files, you can update only when some files have been changed.</p>


  
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